The subject matter relates to a semiconductor memory device, and more particularly to a power-up signal generating circuit, which does not repeatedly activate a power-up signal when noise is applied to an external voltage, and a method for driving the same.
As semiconductor memory technology has advanced, a core voltage applied to a cell has decreased. In some devices a power-up signal generating circuit is provided to generate a stable power-up signal at an initial operation after an external voltage is applied, even for device with differences in process, voltage, or temperature.
The power-up signal generating circuit generates a power-up signal that is activated when a substrate bias voltage VBB reaches a desired level. The power-up signal is used to control voltage levels of internal circuits until internal voltages reach predetermined levels when a setup is completed.
In a dynamic random access memory (DRAM), a PMOS transistor and an NMOS transistor each have a threshold voltage (Vt). Operation of the DRAM is stabilized when the external voltage reaches 2×Vt, which is a sum of the threshold voltage (Vt) of the PMOS transistor and the threshold voltage (Vt) of the NMOS transistor.
In addition, DRAM operation is more stable when the internal voltages generated by external power sources are higher than a predetermined level. Accordingly, it is very important to accurately maintain an activation timing of the power-up signal.
FIG. 1 is a schematic circuit diagram of a conventional power-up signal generating circuit of a semiconductor memory device.
Referring to FIG. 1, the conventional power-up signal generating circuit includes a voltage divider 10, a level detector 20, and a buffer 30. The voltage divider 10 divides an external voltage VDD to output a divided voltage VDD_D. The level detector 20 detects a level of the divided voltage VDD_D and deactivates a level detection signal DT_LV when the level of the divided voltage VDD_D increases above an upper limit reference voltage VT_DIS. The buffer 30 buffers the level detection signal DT_LV to output a power-up signal PWR_UP.
The level detector 20 includes a PMOS transistor PM1 and an NMOS transistor NM1. The PMOS transistor PM1 has a gate connected to a ground voltage (VSS) terminal, a source connected to an external voltage (VDD) terminal, and a drain connected to an output node. The NMOS transistor NM1 has a gate receiving the divided voltage VDD_D, a drain connected to the output node, and a source connected to the ground voltage (VSS) terminal. The level detector 20 outputs the level detection signal DT_LV through the output node.
The voltage divider 10 includes resistors R1 and R2 connected in series between the external voltage (VDD) terminal and the ground voltage (VSS) terminal. The voltage divider 10 outputs the voltage applied to a common node of the resistors R1 and R2 as the divided voltage VDD_D.
An operation of the conventional power-up signal generating circuit will be briefly described.
The voltage divider 10 outputs the divided voltage VDD_D according to a resistance ratio of the resistors R1 and R2. The divided voltage VDD_D has a level of (R2/(R1+R2))×VDD.
The level detector 20 increases the level detection signal DT_LV along the level of the external voltage VDD while the divided voltage VDD_D outputted from the voltage divider 10 is lower than a threshold voltage. Thereafter, when the level of the external voltage increases above the upper limit reference voltage VT_DIS, the NMOS transistor NM1 is turned on, causing the level detection signal DT_LV to decrease to the ground voltage VSS.
The buffer 30 buffers the level detection signal DT_LV to output the power-up signal PWR_UP. Accordingly, the level of the power-up signal PWR_UP increases along the level of increasing external voltage VDD during an initial operation. Thereafter, the power-up signal PWR_UP is deactivated when the level of the external voltage VDD increases above the level of the upper limit reference voltage VT_DIS, at which point it is considered to be stabilized.
Internal blocks of the semiconductor memory device are initialized in response to the power-up signal PWR_UP.
A malfunction of the power-up signal generating circuit shown in FIG. 1 will be described with reference to FIG. 2.
Referring to FIG. 2, as the level of the external voltage VDD increases during the initial operation, the power-up signal generating circuit increases the level of the power-up signal PWR_UP. The power-up signal PWR_UP is deactivated when the level of the external voltage VDD increases above the level of the upper limit reference voltage VT_DIS.
However, when the external voltage VDD is consumed by the internal blocks of the semiconductor memory device, the level of the external voltage VDD may become unstable around the upper limit reference voltage VT_DIS. In this case, the power-up signal PWR_UP is again activated to the level of the external voltage VDD when the level of the external voltage VDD decreases below the level of the upper limit reference voltage VT_DIS. Such a phenomenon may occur repeatedly when the level of the external voltage VDD decreases below the level of the upper limit reference voltage VT_DIS.
The internal blocks of the semiconductor memory device are repeatedly initialized when the power-up signal is repeatedly activated due to instability of the external voltage VDD. When this occurs, the initialization time is increased and current consumption increases due to this undesired operation.